Due to the lack of commercially available GaN substrates, GaN heterostructures are nowadays grown mainly on sapphire and SiC. Si is however a very attractive substrate, gaining more and more interest. Its main advantages are: an acceptable thermal conductivity (half of that of SiC) and its availability in large quantities and large wafer sizes. The most important advantage of Si compared to sapphire and SiC is its very low cost.
Kuykendall (NanoLetters 2003, Vol. 3, No. 8, 1063-10) discloses for instance the formation of GaN nanowires on silicon and sapphire substrates by MOCVD.
However, the growth of high quality epitaxial GaN layers directly on Si is not straightforward.
The high lattice mismatch between Si and GaN results in a high dislocation density in the GaN layer. This high dislocation density can be drastically decreased by adapting suitable growth recipes developed for the growth of GaN on sapphire.
The large difference in thermal expansion coefficient between GaN and Si induces large tensile stress in the GaN film during cooling down from the growth temperature to room temperature, resulting in cracking of the GaN layer. The phenomenon of cracking becomes problematic for layers with a thickness of 1 micron and more, and thus is detrimental for the performance of (opto)electronic devices.
Another problem for the growth of GaN directly on Si is the so-called meltback etching process of Ga and Si. At high temperatures, Ga and Si form an alloy, which initiates a strong and fast etching reaction destroying the substrate and the GaN layer. This results in a very rough surface.
Yet another problem relates to oxide formation on the Si substrate that requires specific attention, such as a careful cleaning just before loading samples in the reactor for the growth of GaN on the substrate.
A further problem for the growth of GaN on Si is the “bowing” of the substrate. When a layer of GaN is formed on Si, strain generated in the layer of GaN will consequently generate strain in the Si substrate. This results in deformation or the so-called ‘bowing’ of the Si substrate.
In patent application WO 03/054939 Aixtron discloses a method for depositing a III-V layer on a non III-V substrate, such as a silicon substrate. A III-V buffer layer or a III-V germination layer is deposited on the substrate by MOCVD.
For the growth of an active GaN layer, Boufaden et al. (Microelectronics Journal 34 (2003) 843-848) proposed to use a thin AlN layer to improve wetting between GaN and a porous Si/Si substrate. The AlN layer would reduce the lattice mismatch between GaN and Si to 2.5%. Also Orita et al. proposed in U.S. Pat. No. 6,344,375 a buffer layer of AlN between a porous Si layer (PS) and a GaN epitaxial layer.
Different methods to reduce cracks and threading dislocations have been reviewed in ‘GaN-Based Devices on Si’, A. Krost and A. Dadgar, Phys. Stat. Sol. (a), Vol. 194, Issue 2, 2002, pp. 361-375.
The different approaches proposed to address the above-mentioned problems can be separated in two categories: those using a completely in-situ growth recipe and those requiring ex-situ processing steps followed by subsequent growth steps. The former group is based on strain engineering, using proper seed-, super- or interlayers, to avoid cracking and to reduce as much as possible the threading dislocation density existing in the active GaN layer. The latter group aims at controlling the geometrical distribution of the thermal cracks and of the threading dislocations. ELOG, Pendeo, Cantilever Epitaxy all lead to high quality areas, while other concentrates all the threading dislocations and/or cracks arising from the stress.